NASA awards next-generation spaceflight computing processor contract to Microchip Technology Inc.

Microchip Technology Inc.

Nasa

NASA’s Jet Propulsion Laboratory in Southern California has selected Microchip Technology Inc. of Chandler, Arizona to develop a High-Performance Spaceflight Computing (HPSC) processor that will provide at least 100 times the computing power of spaceflight computers current. This key capability would advance all types of future space missions, from planetary exploration to lunar and Martian surface missions.

“This state-of-the-art spaceflight processor will have a huge impact on our future space missions and even on technologies here on Earth,” said Niki Werkheiser, director of technology maturation at the Space Technology Missions Directorate at headquarters. NASA in Washington. “This effort will amplify existing spacecraft capabilities and enable new ones and could ultimately be used by virtually all future space missions, all benefiting from more capable flight computing.”

Microchip will build, design and supply the HPSC processor over three years, with the goal of using the processor in future lunar and planetary exploration missions. Microchip’s processor architecture will significantly improve the overall computing efficiency of these missions by allowing computing power to be scalable, based on mission needs. The design will also be more reliable and have higher fault tolerance. The processor will allow spacecraft computers to perform calculations up to 100 times faster than today’s advanced space computers. As part of NASA’s ongoing commercial partnership efforts, the work will be conducted under a $50 million firm fixed price contract, with Microchip contributing significant research and development costs to complete the project.

“We are delighted that NASA has selected Microchip as a partner to develop the next-generation space-qualified compute processor platform.” said Babak Samimi, vice president of Microchip’s Communications business unit. “We are making a joint investment with NASA in a new reliable and transformative computing platform. It will provide full Ethernet networking, advanced AI/machine learning processing, and connectivity support while delivering unprecedented performance boost, fault tolerance, and an unprecedented low-power security architecture. of energy. We will foster an industry-wide ecosystem of single-board computing partners anchored on Microchip’s HPSC processor and space-qualified complete system solutions to benefit from a new generation of computing designs from critical tip optimized for size, weight and power.

Current space-qualified computing technology is designed to handle the most compute-intensive part of a mission—a practice that leads to overdesign and inefficient use of computing power. For example, a mission to the surface of Mars requires high-speed data movement and intense computations during the planetary landing sequence. However, routine mobility and scientific operations require fewer calculations and tasks per second. Microchip’s new processor architecture provides the flexibility for processing power to fluctuate with current operational needs. Some processing functions can also be turned off when not in use, reducing power consumption. This capability will save a large amount of power and improve the overall computing efficiency of space missions.

“Our current spaceflight computers were developed nearly 30 years ago,” said Wesley Powell, NASA’s lead technologist for advanced avionics. “While they have served past missions well, future NASA missions require significantly increased onboard computing capabilities and reliability. The new computing processor will provide the required advances in performance, fault tolerance and flexibility to meet these future mission needs.

Microchip’s HPSC processor may be useful to other government agencies and applicable to other types of future space missions to explore our solar system and beyond, from Earth science operations to Mars exploration and space missions. human moons. The processor could potentially be used for commercial systems on Earth that require advanced computing requirements similar to space missions and are able to continue operations safely if a system component fails. These potential applications include industrial automation, edge computing, time-sensitive Ethernet data transmission, artificial intelligence, and even Internet of Things gateways, which bridge various communication technologies.

In 2021, NASA solicited proposals for a commercial study for an advanced radiation-hardened computer chip with the intention of selecting a vendor for development. This contract is part of NASA’s High-Performance Space Computing project. The HPSC is led by the agency’s Space Technology Mission Directorate Breakthrough Development Program with support from the Science Mission Directorate. The project is led by JPL, a division of Caltech.

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